| abstract |
A page mode multi-level NAND type memory utilizes two different verify levels per data state and is connected to a memory cell and is a first data storage circuit for storing data of an externally input first logic level or second logic level. ; A second data storage circuit connected to the memory cell and storing data of a first logic level or a second logic level read from the memory cell; And a control circuit for controlling the memory cell and the first and second data storage circuits, reproducing externally input data, and writing data into the memory cells. n n NAND memory cells, threshold voltages, data storage circuits, control circuits, latch circuits |