http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-100870009-B1

Outgoing Links

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classificationCPCAdditional http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G02F1-13625
classificationCPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G02F1-1343
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classificationIPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G02F1-136
filingDate 2002-09-04-04:00^^<http://www.w3.org/2001/XMLSchema#date>
grantDate 2008-11-21-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationDate 2008-11-21-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber KR-100870009-B1
titleOfInvention Contact portion of wiring, manufacturing method thereof, and thin film transistor array substrate including same and manufacturing method thereof
abstract First, a gate wiring including a gate line, a gate pad, and a gate electrode is formed on a substrate, and a gate insulating film, a semiconductor layer, an intermediate layer, and a lower film of chromium and an upper film of aluminum or an aluminum alloy are successively deposited, and then a positive photoresist film thereon. Apply. The photosensitive film is irradiated with light through a mask and then developed to form a photosensitive film pattern. The first portion of the photoresist pattern positioned in the channel portion between the source electrode and the drain electrode is made smaller in thickness than the second portion located in the portion where the data line is to be formed, and all other portions and the photoresist in the corner portion of the channel portion are removed. Next, the upper layer exposed to the other part is wet etched, and the lower layer and the semiconductor layer are removed by the dry etching method together with the first part of the photosensitive layer. Subsequently, the photoresist film residue remaining on the surface of the upper film is removed through ashing, and then the source and drain electrodes are separated by etching and removing the upper and lower layers of the channel portion and the intermediate layer pattern thereunder. In this case, both the upper layer and the lower layer are removed by wet etching, and the second photoresist layer is removed after etching the upper layer. Next, a passivation layer, a pixel electrode, an auxiliary gate pad, and an auxiliary data pad are formed.n n n n Aluminum, IZO, Contact Resistance, Chrome, Dry Etch, Wet Etch
priorityDate 2002-09-04-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

Incoming Links

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Total number of triples: 23.