| abstract |
In a semiconductor device and a method of manufacturing the same, the semiconductor device includes first wirings positioned on the lower structure and an insulating pattern formed to apply first wirings on the lower structure. The insulating pattern has voids extending in the horizontal and vertical directions between the first wirings. The semiconductor device may further include a second wiring on which the void corresponds to at least a portion of the semiconductor pattern. The lower structure may further include a conductive element at least partially corresponding to the void. Therefore, parasitic capacitance generated horizontally between the first wirings and parasitic capacitance generated vertically between the second wiring and the conductive element can be reduced. |