http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-100799133-B1
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_1a492183be65153abfa7dec00d51c816 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-28123 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-053 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66621 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-4236 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-3065 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78 |
| filingDate | 2006-08-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2008-01-29-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_8fbf82af6d1763a393b15f08504be5eb http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_dd315542802e4b6bd322a9f26d93305f |
| publicationDate | 2008-01-29-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | KR-100799133-B1 |
| titleOfInvention | Method of manufacturing recess gate of semiconductor device |
| abstract | The present invention is to provide a method for manufacturing a recess gate of a semiconductor device capable of suppressing leakage current by minimizing the size of the peaks generated when the recess pattern is formed. Selectively etching the active region of the substrate to form a recess pattern; post-processing the recess pattern using plasma of a mixed gas in which fluorine-based gas, oxygen gas, and inert gas are mixed; and the recess pattern Forming a gate pattern on the above, the present invention described above by using a fluorine radical in the post-treatment to change the shape of the recess pattern from a pointed shape to a flat round bottom shape and at the same time minimize the height of the peak Thus, a three-dimensional recess gate in which leakage current is suppressed can be applied to a cell of a highly integrated DRAM of 80 nm or less. There are effective. |
| priorityDate | 2006-08-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 32.