http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-100789606-B1
Outgoing Links
Predicate | Object |
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classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-761 |
classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-76 |
filingDate | 2006-09-26-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
grantDate | 2007-12-27-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
publicationDate | 2007-12-27-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
publicationNumber | KR-100789606-B1 |
titleOfInvention | Semiconductor device and manufacturing method thereof |
abstract | In the conventional semiconductor device, there is a problem that it is difficult to reduce the device size due to the diffusion of the P-type diffusion layer constituting the isolation region in the horizontal direction. In the semiconductor device of the present invention, an N-type epitaxial layer 8 is formed on the P-type single crystal silicon substrate 6. The substrate 6 and the epitaxial layer 8 are partitioned into a plurality of element formation regions by the separation region 3. The isolation region 3 is formed by connecting the P-type buried diffusion layer 47 and the P-type diffusion layer 48. The P-type buried diffusion layer 47 forms the P-type junction region with the N-type buried diffusion layers 7 and 30. On the other hand, the P type diffusion layer 48 forms the N type diffusion layers 19 and 40 and the PN junction region. By this structure, the diffusion of the P-type buried diffusion layer 47 and the P-type diffusion layer 48 is suppressed in the horizontal direction, and the device size can be reduced.n n n n Monocrystalline Silicon Substrates, N-type buried diffused layers, epitaxial layers, N-channel DMOS transistors, contact holes, photolithography, barrier metal films, back gate electrodes |
priorityDate | 2005-09-27-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 15.