http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-100772704-B1
Outgoing Links
| Predicate | Object |
|---|---|
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76232 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-762 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-762 |
| filingDate | 2005-09-29-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2007-11-02-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate | 2007-11-02-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | KR-100772704-B1 |
| titleOfInvention | Method for manufacturing a semiconductor device having a tapered trench |
| abstract | SUMMARY OF THE INVENTION The present invention provides a method for manufacturing a semiconductor device capable of preventing voids of a gap fill insulating film gap-filled in a device isolation trench and at the same time ensuring bottom flatness of a recess pattern. First etching the semiconductor substrate to form an upper region having an etched tapered shape; Second etching the semiconductor substrate under the upper region to form an intermediate region having a profile angle larger than that of the upper region; Tertiary etching the semiconductor substrate below the intermediate region to form a lower region having an etched tapered shape; Forming an isolation layer buried in the trench including the upper region, the middle region and the lower region; And etching the active region defined by the trench to a predetermined depth to form a recess pattern for the recess gate.n n n n Recess gate, recess pattern, trench, STI, profile angle, tapered etching |
| priorityDate | 2005-09-29-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 17.