http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-100768729-B1
Outgoing Links
| Predicate | Object |
|---|---|
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/Y02D10-00 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F13-1689 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-4093 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F13-16 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-4093 |
| filingDate | 2001-09-17-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2007-10-22-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate | 2007-10-22-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | KR-100768729-B1 |
| titleOfInvention | Clock Synchronous Dynamic Memory and Clock Synchronous Integrated Circuits |
| abstract | The synchronous dynamic memory has a clock input buffer for receiving an external clock and outputting an external clock of an input, a command input buffer for receiving a command, an address input buffer for receiving an address, and a data input buffer for receiving data. . In the normal mode of operation, the clock input buffer supplies the clock to the command, address and data input buffers. In a data retention mode, such as a power down mode, the clock input buffer supplies the clock to the command input buffer rather than the address and data input buffer. |
| priorityDate | 2000-12-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 37.