http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-100745986-B1
Outgoing Links
| Predicate | Object |
|---|---|
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/B82Y40-00 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-28 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76808 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-28 |
| filingDate | 2004-12-08-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2007-08-06-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate | 2007-08-06-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | KR-100745986-B1 |
| titleOfInvention | Method for manufacturing dual damascene wiring of microelectronic device using filler containing porous generating material |
| abstract | Provided is a method for manufacturing dual damascene wiring of a microelectronic device capable of minimizing damage to an interlayer insulating layer by using a filler including a porous material. The dual damascene manufacturing method fills the via with a filler including a porogen, and then partially fills the via and the interlayer insulating layer to form a trench to be connected to the via and to form a wiring. Subsequently, the pore-generating material of the filler remaining in the via is removed to form pores in the filler, and then the pore-filled filler is removed, and the trenches and vias are filled with the wiring material to complete the dual damascene wiring.n n n n Dual damascene, interlayer dielectric damage, porous material |
| priorityDate | 2004-12-08-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 45.