http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-100720095-B1
Outgoing Links
| Predicate | Object |
|---|---|
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G02F1-136254 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G02F1-13458 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-124 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1255 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1288 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G02F1-136 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G02F1-1362 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-32134 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-32136 |
| classificationIPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-13 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-77 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-12 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G02F1-136 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-3213 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-84 |
| filingDate | 2000-11-07-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2007-05-18-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate | 2007-05-18-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | KR-100720095-B1 |
| titleOfInvention | Thin film transistor array substrate and manufacturing method thereof |
| abstract | First, an auxiliary layer for a pad is formed on a pad portion on which a gate line, a gate electrode, and a gate pad in a horizontal direction including a gate line, a gate electrode, and a gate pad are formed on the substrate by stacking and patterning an aluminum-based conductive material. , A semiconductor layer and an ohmic contact layer are sequentially formed. Subsequently, a metal line such as chromium is laminated and patterned to form a data line including a data line crossing the gate line, a source electrode, a drain electrode, and a data pad having contact holes on the pad auxiliary layer. The protective film is then stacked and patterned to form contact holes exposing the drain electrode, gate pad, and data pad. At this time, the pad auxiliary layer is exposed through the contact hole of the data pad. Subsequently, the IZO is stacked and patterned to form a pixel electrode, an auxiliary gate pad, and an auxiliary data pad electrically connected to the drain electrode, the gate pad, and the data pad and an auxiliary layer for the pad below. As such, by forming an auxiliary layer for pads based on aluminum, the contact resistance of the pad part may be minimized during the liquid crystal panel inspection. |
| priorityDate | 2000-11-07-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 30.