http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-100680473-B1
Outgoing Links
| Predicate | Object |
|---|---|
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2029-0411 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/B65D2585-00 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F11-1068 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/A61G17-007 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/A61G17-08 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-1006 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C16-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F12-00 |
| filingDate | 2005-04-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2007-02-08-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate | 2007-02-08-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | KR-100680473-B1 |
| titleOfInvention | Flash memory device with reduced access time |
| abstract | The present invention relates to a flash memory device having reduced access time. The flash memory device according to the present invention performs an error detection and correction operation simultaneously with encoding or decoding signals transmitted and received with a host device. It can be simplified, and its access time is reduced, so that the performance of the entire system including the flash memory device can be improved.n n n n FSM check unit, main combination circuit, sub combination circuit, error check unit, error comparison unit |
| priorityDate | 2005-04-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 32.