http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-100673011-B1
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c16d2144a81bfa32a665dca1e93c3d37 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B41-49 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-105 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B41-40 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B99-00 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8247 |
| filingDate | 2005-08-12-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2007-01-24-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_11efd5149b01a152f3d7f75edb3a9f06 |
| publicationDate | 2007-01-24-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | KR-100673011-B1 |
| titleOfInvention | NOR flash memory device and manufacturing method thereof |
| abstract | A NOR flash memory device and a method of manufacturing the same are provided. The device includes active regions formed in a semiconductor substrate having a cell array region, a high voltage transistor region, and a low voltage transistor region, a gate structure across the active regions, a source region and a drain region formed in the active regions adjacent to the gate structure, and a gate structure. It includes a lower spacer formed on both sides of the. In this case, the lower spacer fills the space between the gate structures in the upper portion of the source region of the cell array region, and is formed of a silicon oxide layer. |
| priorityDate | 2005-08-12-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 24.