http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-100667865-B1
Outgoing Links
| Predicate | Object |
|---|---|
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-1072 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-407 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-1039 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-406 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-406 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-407 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C7-10 |
| filingDate | 2000-11-27-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2007-01-12-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate | 2007-01-12-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | KR-100667865-B1 |
| titleOfInvention | Semiconductor devices |
| abstract | The dynamic memory requires a refresh operation to maintain information in the memory cell. As a result, contention occurs between access (external access) to the dynamic memory other than the refresh and the access for refresh, and performance deterioration occurs.n n n Pipeline the dynamic memory, make the pipeline frequency CLK of the pipeline dynamic memory PDRAM higher than the external access frequency CLK1, and pipeline the dynamic memory. An access required for the refresh operation is performed to the pipeline dynamic memory at an empty slot (timing at which an external access is not necessarily issued).n n n The refresh to the internal dynamic memory becomes an internal operation, and refreshing is unnecessary at the external access timing, which is convenient to use and high speed.n n n n Memory cell, row decoder, memory circuit, access control circuit |
| priorityDate | 1999-12-08-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 36.