http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-100666184-B1
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c16d2144a81bfa32a665dca1e93c3d37 |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2211-5642 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-24 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-30 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-5628 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-5642 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-0483 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-12 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C16-04 |
| filingDate | 2006-02-02-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2007-01-09-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_907037dd29161f4f7d2e1200dd2c055f http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_6b92c2b08c152c0dd92dbfc831a93573 |
| publicationDate | 2007-01-09-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | KR-100666184-B1 |
| titleOfInvention | 3-level nonvolatile semiconductor memory device in which lower bit lines and upper bit lines share a voltage control block |
| abstract | A three-level nonvolatile semiconductor memory device having a lower bit line and an upper bit line sharing a voltage control block is disclosed. The nonvolatile semiconductor memory device of the present invention includes three-level memory cells that can be controlled at three threshold voltage levels and a page buffer for controlling them. Two sets of three-level memory cells can map 3 bits of data. According to the nonvolatile semiconductor memory device of the present invention, high integration and reliability are obtained. In the nonvolatile semiconductor memory device of the present invention, a switch for controlling the electrical connection of the even bit lines and the odd bit lines is controlled by an independent control signal. Therefore, in the nonvolatile semiconductor memory device of the present invention, the upper bit lines and the lower bit lines share the voltage control block, which is significantly advantageous over the comparative example in terms of layout. |
| priorityDate | 2006-02-02-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 23.