http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-100638988-B1
Outgoing Links
| Predicate | Object |
|---|---|
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02532 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02598 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-42356 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76224 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-665 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-28 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336 |
| filingDate | 2004-12-23-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2006-10-26-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate | 2006-10-26-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | KR-100638988-B1 |
| titleOfInvention | Semiconductor device and its planarization method using epitaxial process |
| abstract | BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device using an epitaxial process that does not require a planarization and cleaning process before contact formation and a planarization method thereof. A method of planarization of a semiconductor device using an epitaxial process according to the present invention includes the steps of: a) depositing a pad oxide film and a pad nitride film on a semiconductor substrate; b) forming a device isolation layer (STI) by forming and filling an STI trench region; c) stripping the pad nitride film and depositing a gate oxide film and a gate poly on the exposed front surface; d) patterning and etching the gate poly to form a gate, and depositing a nitride film on both sidewalls of the gate to form a spacer; e) implanting ions into the active region to form a source / drain; f) depositing on the source / drain using an epitaxial process to form an epitaxial layer; g) forming silicide on the epitaxial layer and the gate; And h) depositing an intermetallic material on the exposed front surface. According to the present invention, by minimizing the step difference between the source-gate-drain and the STI using an epitaxial process, the planarization process and other cleaning processes do not need to be performed, thereby contributing to the cost reduction of semiconductor device production.n n n n Planarization, epitaxial process, MOSFET, CMP |
| priorityDate | 2004-12-23-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 25.