http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-100620705-B1
Outgoing Links
| Predicate | Object |
|---|---|
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-3011 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-0002 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-5252 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-82 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-82 |
| filingDate | 2004-12-31-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2006-09-13-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate | 2006-09-13-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | KR-100620705-B1 |
| titleOfInvention | Antifuse with uniform thickness of dielectric and its manufacturing method |
| abstract | The present invention relates to a structure of an antifuse capable of maintaining thickness uniformity of an amorphous silicon layer constituting an antifuse and a method of manufacturing the same, wherein the antifuse of the present invention is (a) an insulating layer applied on an underlayer A via formed in the (b) bottom barrier metal layer in contact with the inner wall of the via and the top surface of the insulating layer, (c) a fill layer in contact with the bottom barrier metal layer and filling the via, and (d) the top and bottom of the fill layer An amorphous silicon dielectric layer in contact with a portion of the barrier metal layer, and (e) an upper barrier metal layer formed over the amorphous silicon dielectric layer. Here, the filling layer is applied by applying tungsten metal to the entire substrate or wafer, planarizing the tungsten metal layer by the CMP polishing process so that only the tungsten metal layer remains in the via, and then etching the tungsten metal layer remaining only in the via with, for example, an H 2 O 2 etch cleaner. The tungsten metal layer may be formed in such a manner that the tungsten metal layer has a recess of a predetermined depth. The filling layer compensates for the surface curvature due to the vias by filling the vias, so that the thickness of the filling layer can be maintained even if the amorphous silicon dielectric layer is formed in the vias. Titanium silicides can be easily made in contact with the upper and lower barrier metal layers.n n n n Antifuse, antifuse, amorphous silicon, FPGA, via |
| priorityDate | 2004-12-31-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 31.