http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-100586770-B1
Outgoing Links
| Predicate | Object |
|---|---|
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78645 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78648 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-2807 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-49 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66484 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7831 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-49 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-08 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-088 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-786 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8234 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-02 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-76 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-12 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-762 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-28 |
| filingDate | 2002-05-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2006-06-08-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate | 2006-06-08-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | KR-100586770-B1 |
| titleOfInvention | Intermediate structure for dual gate logic device, method of forming the intermediate structure |
| abstract | The present invention is characterized by providing a double or dual gate logic device comprising a gate conductor that is constantly self-aligned and has a constant width channel. In addition, the method of the present invention provides a method for selectively etching germanium containing gate conductor materials without efficiently etching adjacent silicon channel materials. By this method, the gate conductor can be enclosed inside the dielectric shell without changing the length of the silicon channel. Single crystal silicon wafers are used as the channel material. Pillars, or stacks, of self-aligned dual gate MOSFETs are created by etching through the parallel arrangement of redundant germanium containing gate conductor regions. By vertically etching through both regions of the gate conductive material and the dielectric insulating material, essentially a fully self aligned dual gate stack is realized. A method has been described in which a gate conductor material can be selectively etched without etching the channel material. |
| priorityDate | 2001-06-12-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 65.