http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-100571331-B1
Outgoing Links
| Predicate | Object |
|---|---|
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K2005-00286 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03L7-0818 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C8-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-22 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03L7-0814 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03L7-0816 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K5-135 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K5-133 |
| classificationIPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03K5-00 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03L7-081 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03K5-135 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C8-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C7-22 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03K5-13 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-822 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-4076 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-407 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F1-10 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03L7-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-04 |
| filingDate | 2000-06-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2006-04-17-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate | 2006-04-17-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | KR-100571331-B1 |
| titleOfInvention | Delay circuit and semiconductor integrated circuit having same |
| abstract | BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit equipped with a delay circuit and a DLL circuit, and aims to accurately perform a phase comparison by adjusting a delay time of a clock signal with good accuracy.n n n The delay circuit includes a plurality of cascaded interpolation circuits that operate as phase adjustment circuits or delay stages. Since the interpolation circuit is used, the delay time can be adjusted with good accuracy. The phase comparison circuit compares the phase of the reference clock signal with the phase of the delayed clock signal. The control circuit provides ratio information to each interpolation circuit based on the comparison result of the phase comparison circuit, and performs control to match the phase of the reference clock signal and the delayed clock signal. Since the phase adjustment of the delayed clock signal is performed by controlling the delay circuit using a plurality of interpolation circuits, the minimum unit of fine adjustment can be made small. That is, the phase is reliably adjusted even in a semiconductor integrated circuit to which a high frequency reference clock signal is supplied. |
| priorityDate | 1999-10-12-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 67.