http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-100568452-B1
Outgoing Links
| Predicate | Object |
|---|---|
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2223-54426 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2223-54453 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L28-91 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-0002 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2223-5446 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-315 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B99-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-09 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-544 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-108 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8242 |
| filingDate | 2004-09-23-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2006-04-07-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate | 2006-04-07-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | KR-100568452-B1 |
| titleOfInvention | A method of manufacturing a semiconductor device having an alignment key and a semiconductor device manufactured thereby. |
| abstract | Provided are a method of manufacturing a semiconductor device having an alignment key, and a semiconductor device manufactured thereby. According to one aspect, the method of manufacturing a semiconductor device includes preparing a semiconductor substrate having a scribe lane region and a cell region. An etch stop pattern and a gate pattern are formed on the scribe lane region and the cell region, respectively. A first interlayer insulating layer may be formed to cover the etch stop pattern and the gate pattern. A preliminary alignment key pattern and a bit line pattern are respectively formed on the scribe lane region and the first interlayer insulating layer of the cell region. A second interlayer insulating layer may be formed to cover the preliminary alignment key pattern and the bit line pattern. The second interlayer insulating layer and the first interlayer insulating layer are patterned to expose the etch stop pattern, thereby forming an alignment key pattern in the scribe line region and forming a storage node contact opening in the cell region.n n n n Alignment Key, Storage Node, Mesa, Trench, Step |
| priorityDate | 2004-09-23-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 31.