http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-100566466-B1
Outgoing Links
| Predicate | Object |
|---|---|
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2211-565 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2211-5647 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2211-5643 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2211-5642 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2211-5641 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2211-5621 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-1006 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-10 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-12 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-06 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-32 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-3427 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-3418 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-3431 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-3454 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-3459 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-5628 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-5621 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-5642 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-34 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C16-06 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-56 |
| filingDate | 1995-11-07-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2006-03-31-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate | 2006-03-31-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | KR-100566466-B1 |
| titleOfInvention | Semiconductor memory device |
| abstract | The present invention relates to a technology effective by using a plurality of pieces of stored information in an electrically nonvolatile memory device, wherein the threshold voltage of a memory cell is changed over time due to a deviation distribution shape as the power supply voltage of the LSI decreases. In order to solve the problem of exceeding the voltage margin range and to cause a malfunction, the memory cell can be read by setting the threshold value of the memory cell to two or more steps and changing the level of the word line to two or more steps. A nonvolatile memory device configured to store two or more bits of data in one memory cell by performing a predetermined operation on a binary data register holding input data and several bits of the input data. Leads in data conversion logic circuits and memory cells converting to chopped data according to their combination The data was chopped in a configuration that includes a logical inversion circuit for converting the original binary data on the.n n n By doing so, it is possible to realize a miniaturized memory type nonvolatile memory device capable of minimizing the increase in the circuit scale and enabling high-precision write, read and erase operations in a short time, and at the same time, the threshold variation distribution shape of the memory device. A nonvolatile memory device capable of steep operation and stable operation at low voltage can be realized.n n n n Chopped data, chopped memory, refresh |
| priorityDate | 1995-01-31-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 51.