http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-100555572-B1

Outgoing Links

Predicate Object
assignee http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c16d2144a81bfa32a665dca1e93c3d37
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http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C29-46
classificationIPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C29-00
filingDate 2004-09-10-04:00^^<http://www.w3.org/2001/XMLSchema#date>
grantDate 2006-03-03-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_b8f49048df5d25a7fdfc65b3614d3f5d
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_055259eab5b8cc10443cd68e5620f50c
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publicationDate 2006-03-03-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber KR-100555572-B1
titleOfInvention Test mode signal generation circuit and test mode setting method of memory device
abstract A memory device capable of setting a test mode is disclosed. The memory device may include a test mode entry signal generator for generating a test mode entry signal TMSET indicating a test mode entry of the memory device according to a combination of an address signal and a command signal, in response to the test mode entry signal. An input control unit for outputting a test mode latch clock signal TCLK, which is a clock signal for synchronizing a memory device operating in a test mode, and a test mode setting signal PSET instructing generation of a test mode signal, and the test mode And a test mode signal generator for sequentially generating a test mode signal in synchronization with the test mode latch clock signal in response to a setting signal.n n n n Memory device, test mode
isCitedBy http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8214171-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-100891304-B1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-100932868-B1
priorityDate 2004-09-10-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

Incoming Links

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Total number of triples: 21.