http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-100552811-B1
Outgoing Links
| Predicate | Object |
|---|---|
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76873 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-28 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76862 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76843 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-28 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-768 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-4763 |
| filingDate | 2003-12-31-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2006-02-22-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate | 2006-02-22-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | KR-100552811-B1 |
| titleOfInvention | Metal wiring formation method of semiconductor device |
| abstract | Stacking a first etch stop film, an interlayer insulating film, a second etch stop film, and a wiring insulating film on a semiconductor substrate having a predetermined substructure, forming a contact hole pattern on the wiring insulating film, and exposing the contact hole pattern as a mask. Forming a contact hole by etching the first wiring insulating film, the first etch stop film, and the interlayer insulating film, removing the contact hole pattern, and then forming a trench pattern on the wiring insulating film, and using the trench pattern as a mask. Etching to form a trench, removing the trench pattern, removing the exposed first etch stop layer and the second etch stop layer, depositing a barrier metal layer on the inner wall and the underlying structure of the contact hole and the trench, sputtering process Forming a plurality of grooves in the barrier metal film by depositing, depositing a metal seed film on the barrier metal film, and contact holes Depositing a thin metal film in the trenches, the metallic chemical polishing of the metal thin film above the wiring insulating film by a process, the metal seed layer and the metal wiring formation method of a semiconductor device including the step of removing the barrier metal film.n n n n Dual damascene, barrier metal film, groove, metal wiring |
| priorityDate | 2003-12-31-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 19.