http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-100498195-B1
Outgoing Links
| Predicate | Object |
|---|---|
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-344 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-3445 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-107 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-16 |
| classificationIPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C16-34 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C16-16 |
| filingDate | 2002-12-24-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2005-06-29-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate | 2005-06-29-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | KR-100498195-B1 |
| titleOfInvention | Non-volatile semiconductor memory device and method of performing erasure sequence therefor |
| abstract | A nonvolatile semiconductor memory device includes a plurality of blocks including a plurality of memory cells to be erased at one time and a decoder to select the memory cells, a sense amplifier, and an address of the memory cells when erased, and all selected memory cells. And an address control circuit for controlling a sequence of erasing after writing before erasing, wherein the block latches a selection signal of the block upon writing before erasing, and erases all blocks on which the selection signal is latched upon erasing. Each block having a block decoder to select at the same time and the selection signal is latched is configured to be controlled to be collectively erased by the address control circuit. |
| priorityDate | 2001-12-25-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 18.