| Predicate |
Object |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/Y10S257-90 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-6653
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823481
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-665
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66515
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-41775
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66628
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-41783
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823418
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76224 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8234
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-762
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-76
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-417
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-28
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78 |
| filingDate |
2001-12-26-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2005-04-08-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate |
2005-04-08-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
KR-100481657-B1 |
| titleOfInvention |
A semiconductor device and manufacturing method thereof |
| abstract |
Provided is a semiconductor device having a large contact area on the source / drain region and good device isolation characteristics regardless of the miniaturization of transistors. The cross-sectional shape of the gate sidewall insulating film is L-shaped and inverted L-shaped to cover a part of the silicon substrate surface near the gate electrode, and a silicon single crystal layer selectively epitaxially grown from the source / drain region to cover a part of the silicon substrate surface. By extending to the top surface of the gate sidewall insulating film, a contact area on the source / drain region is secured regardless of the miniaturization of the transistor, thereby reducing the series resistance of the transistor, and providing a semiconductor device comprising a high performance MOS transistor having an elevated source / drain structure. do. |
| priorityDate |
2000-12-27-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |