| abstract |
In order to wire the signal and power lines of circuits, devices and other elements on silicon wafers, as well as active and passive devices, a method of forming copper wiring conductors is presented. The invention presented herein involves a chemical vapor deposition (CVD) process, typically with copper as the raw material of the wiring conductor material, with the catalyst. The trenches, via holes, contacts, and wide passives, as well as the wide trenches and holes for the power lines and power lines, are described and disclosed herein. Another method presented here is to fill small depressions, such as narrow, deep trenches and small diameter, deep holes, by means of a copper CVD method using a catalyst, wherein a thin, flat top surface thin film is used for wet or dry etchback or hot plasma etchback processes. By forming a very thin film on the flat top surface so that it can be removed in preparation for subsequent process steps. This eliminates the need for very expensive chemical mechanical polishing (CMP) methods. |