http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-100455011-B1
Outgoing Links
| Predicate | Object |
|---|---|
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F7-49921 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-3001 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F7-5443 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F17-16 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F7-49921 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F7-57 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-30014 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-30025 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F9-302 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F17-16 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F9-305 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F7-544 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F7-38 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F17-10 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F7-57 |
| filingDate | 1997-11-29-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2004-12-17-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate | 2004-12-17-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | KR-100455011-B1 |
| titleOfInvention | Processor which can favorably execute a rounding process composed of positive conversion and saturated calculation processing |
| abstract | BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a processor that performs processing in accordance with an instruction sequence stored in a ROM or the like, and performs fast processing of converting coded data into unsigned data and saturation operation processing rounded at appropriate bits at high speed. In order to do this, when the constant value saturation calculation instruction "MCSST D1" is decoded, the accumulation result dedicated register 6 outputs the holding value on the path P1. The comparison circuit 22 compares the holding value of the dedicated result register 6 with the magnitude of the 32-bit signed integer (0x000000FF). The government judging circuit 23 determines whether the eighth bit of the value held by the dedicated result register 6 is on. The multiplexer 24 selects any one of the holding value of the dedicated register 6 of the accumulation result, the maximum value "0x0000_0000" generated by the constant generation circuit 21, and the zero value "0x0000_0000" in which the constant value saturation operation instruction "MCSST D1" has occurred. Output on the data bus 18. |
| priorityDate | 1996-11-29-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 27.