http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-100440561-B1
Outgoing Links
| Predicate | Object |
|---|---|
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-1006 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2211-5642 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2211-5641 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2211-5621 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-5635 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-3454 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-3459 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-5628 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-5621 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-5642 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-005 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-3481 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-26 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-12 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-06 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C17-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C16-06 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C16-02 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-56 |
| filingDate | 1997-04-29-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2004-10-12-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate | 2004-10-12-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | KR-100440561-B1 |
| titleOfInvention | Nonvolatile semiconductor memory device |
| abstract | Volatile semiconductor memory device. In order to enable storing information of four digits (two bits) in one memory cell of a nonvolatile semiconductor memory device, three different voltages are sequentially applied to a word line (1 bit) of write data corresponding to a quadrature (2 bits) information to be written every three write operations at this time, (Two bits) of information are written into one memory cell, thereby increasing the storage capacity of the flash memory. In the information lead, three different voltages are applied to the word lines Three types of binary (1-bit) pieces of information read out are synthesized by the read data conversion circuit, and the storage information of the memory cell is converted into 2-bit information.n n n With such a configuration, it is possible to increase the capacity of the nonvolatile semiconductor memory device such as a flash memory, and at the same time, it is possible to suppress an increase in the chip area due to the increase in capacity. |
| priorityDate | 1996-05-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 58.