http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-100433751-B1
Outgoing Links
| Predicate | Object |
|---|---|
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H04B2201-70707 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H04B1-70755 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H04L7-0054 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03L7-00 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H04L7-02 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H04L7-08 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03L7-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H04L25-40 |
| filingDate | 1996-07-31-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2004-08-18-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate | 2004-08-18-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | KR-100433751-B1 |
| titleOfInvention | Fast acquisition bit timing loop method and apparatus |
| abstract | The present invention relates to an apparatus for acquiring and adjusting bit synchronization in a direct sequential frequency spreading receiver. In one embodiment of the present invention, by sampling the clocking circuit as late as 1/2 of the clock period and inverting the clocking circuit selectively to combine the omission and inversion of one period, To adjust bit synchronization. Further, in another embodiment of the present invention, the synchronization circuit prevents components from being integrated and overflowed by down-shifting both the subtotal and the input data when necessary. |
| priorityDate | 1995-07-31-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
| Predicate | Subject |
|---|---|
| isDiscussedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/substance/SID426135032 http://rdf.ncbi.nlm.nih.gov/pubchem/compound/CID7156993 |
Total number of triples: 18.