http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-100419901-B1
Outgoing Links
| Predicate | Object |
|---|---|
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02126 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02167 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-0217 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-31144 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76807 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76829 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-28 |
| filingDate | 2001-06-05-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2004-03-04-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate | 2004-03-04-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | KR-100419901-B1 |
| titleOfInvention | Method of fabricating semiconductor device having dual damascene interconnection |
| abstract | A method of manufacturing a semiconductor device having dual damascene wiring is provided. This method uses the remaining photoresist as an etch mask by leaving the photoresist with a material film capable of inhibiting the catalysis of acid generated in the exposed photoresist. First, an etch stop film and an interlayer insulating film are sequentially formed on the semiconductor substrate on which the lower wiring is formed. Subsequently, the interlayer insulating layer is patterned to form a via hole in which an etch stop layer is exposed on the lower wiring, and a second photoresist pattern 32 exposing the interlayer insulating layer is formed across the via hole. At this time, photoresist remains on the etch stop layer in the via hole. Subsequently, the upper portion of the interlayer insulating film is partially etched using the second photoresist pattern and the remaining photoresist as an etching mask to form wiring grooves passing through the via holes. The second photoresist pattern and the photoresist remaining in the via hole are removed, and the etch stop layer exposed in the via hole is removed to expose the lower wiring. |
| priorityDate | 2001-06-05-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 22.