| Predicate |
Object |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-1075
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-005
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-103
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-1045
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-1072 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-41
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-401
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C7-10
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C7-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F12-08 |
| filingDate |
1998-09-15-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2003-11-28-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate |
2003-11-28-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
KR-100396538-B1 |
| titleOfInvention |
Semiconductor integrated circuit device |
| abstract |
The semiconductor integrated circuit device includes a main memory unit and a sub memory unit including a plurality of memory cell groups, and bidirectional data transfer is performed between an arbitrary region of the main memory unit and each of the plurality of memory cell groups, and the plurality of memory cell groups. Each function as an independent cache memory. Thus, the semiconductor integrated circuit device of the present invention has a main memory suitable for being accessed from a plurality of data processing devices. |
| priorityDate |
1997-09-16-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |