| Predicate |
Object |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-48247
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-48227
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-48091
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-15311 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G01R31-318536
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C29-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G01R31-318505 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-04
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L25-18
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L25-07
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L25-065
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-822
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C29-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G01R31-3185
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G01R31-28
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-66 |
| filingDate |
2000-07-13-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2003-07-22-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate |
2003-07-22-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
KR-100392300-B1 |
| titleOfInvention |
Semiconductor device |
| abstract |
Each chip has a register such as a BSR in addition to the core logic. The TAPC for controlling the registers is provided only on the chip of the first stage, and connects the signal lines of the test command / data output and the input signal lines of the boundary scan test in a loop form through the wires connecting the chips. The other signal line used for the test is distributed from the output signal line of the chip of the first stage. As a result, the number of chips and the area of the chip without a TAPC can be reduced at the same time with a small number of pins and at the same time. With the above configuration, in the stack device formed by integrally sealing a plurality of chips, it is possible to execute a boundary scan test with a small number of pins at once. |
| priorityDate |
1999-11-09-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |