http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-100377625-B1
Outgoing Links
| Predicate | Object |
|---|---|
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F13-14 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K19-01759 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C7-00 |
| filingDate | 2001-01-09-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2003-03-26-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate | 2003-03-26-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | KR-100377625-B1 |
| titleOfInvention | Two way latch circuit for data processing |
| abstract | The bidirectional latch circuit for data processing according to the present invention comprises first to third inverters for inverting an input signal and outputting the same, and inputting a microprocessor while buffering the signal according to the output signal inverted from the third inverter. A fourth inverter outputting a signal after delaying the signal for a predetermined time according to the bus size of the peripheral device; A deflip-flop for outputting data on a signal of a peripheral device after the chip selector is selected according to the signal inverted from the second inverter; And a fifth inverter outputting data output from the flip-flop to the microprocessor, but delaying the output of the data for a predetermined time according to the bus size of the microprocessor according to the signal inverted from the first inverter and outputting the data. It is composed by connection.n n n According to the present invention, a buffer and a latch circuit are respectively configured at the input and output terminals such that only the buffer operation is performed when the data is output from the microprocessor to the peripheral device and the latch operation is performed only when the data is output from the peripheral device to the microprocessor. In addition, the complexity of the circuit configuration, which has emerged as a conventional problem, and of course, eliminates unnecessary signals, thereby enabling faster data processing speeds of the microprocessor and its peripheral devices. |
| priorityDate | 2001-01-09-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 27.