http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-100368628-B1
Outgoing Links
| Predicate | Object |
|---|---|
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-09 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L28-91 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-0335 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-482 |
| classificationIPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-02 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-108 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-04 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8242 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-822 |
| filingDate | 1997-05-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2003-10-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate | 2003-10-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | KR-100368628-B1 |
| titleOfInvention | Dram cell with stacked capacitor self-aligned to bitline |
| abstract | A semiconductor chip having a uniform topology of the present invention includes a memory cell having a stacked capacitor self-aligned with a bit line. The thick insulator on the interconnect wiring on the bit line and chip support circuits provides a uniform topology and acts to self-align the capacitor and the bit line. The bit lines and the support circuit interconnect wiring are both formed of the same level of metal but are patterned in a separate masking step. The stacked capacitors are spaced from each other by less than a minimum dimension of the photolithographic system used for fabrication. |
| priorityDate | 1996-07-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 26.