| abstract |
Gate insulator with high dielectric constant (k greater than 7), low overlap capacitance (0.35fF / μm or less), and shorter than lithography-defined gate length (sub-lithography, for example 0.1 μm or its A method of manufacturing a metal oxide semiconductor field effect transistor (MOSFET) having a channel length of the following is provided. This method includes a damascene processing step and a chemical oxide removal (COR) step. The COR step forms a wider taper on the pad oxide layer, which, when combined with a high k value gate insulator, compares to a MOSFET device formed using conventional Complementary Metal Oxide Semiconductor (CMOS) technology. Low overlap capacitance, short channel length and better device performance. |