| abstract |
The semiconductor chip package according to the present invention is a wafer level package including a ground metal layer adjacent to the signal metal layer so as to ensure operating characteristics of the high-speed semiconductor chip and to minimize inductance and parasitic variables caused by the signal line. And a semiconductor chip having an active surface on which a ground electrode pad and an on-chip circuit are formed, a first insulating layer formed to expose a signal electrode pad and a ground electrode pad on the active surface, and directly contacting the ground electrode pad on the first insulating layer. A first metal layer in the form of a plate, comprising a ground metal layer, a second insulating layer formed directly over the first metal layer and including a ground contact portion for the ground electrode pad and a signal contact portion for the signal electrode pad, and a ground contact portion. Ground pattern connected to the ground electrode pad through the signal pattern connected to the signal electrode pad through the signal contact And a second metal pattern layer formed directly on the second insulating layer, and electrically connected to the ground pattern and the signal pattern of the second metal pattern layer, respectively, to provide a passage through which the semiconductor chip is electrically connected to the outside. It includes an external connection. The first insulating layer, the first metal layer, the second insulating layer, and the second metal pattern layer may be formed of a plurality of layers. |