http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-100298995-B1
Outgoing Links
| Predicate | Object |
|---|---|
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G02F1-1309 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G02F1-136204 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G3-3648 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G3-006 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G02F1-136286 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G09F9-30 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G02F1-1368 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G02F1-1362 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G02F1-136 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G02F1-1345 |
| filingDate | 1998-11-14-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2001-09-06-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate | 2001-09-06-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | KR-100298995-B1 |
| titleOfInvention | Liquid Crystal Display and Inspection Method |
| abstract | The liquid crystal display device includes an array substrate; An opposing substrate facing the array substrate; And a liquid crystal layer interposed between the array substrate and the opposing substrate, the array substrate comprising: a plurality of pixel electrodes arranged in a matrix in a display area; A plurality of gate lines; A plurality of source lines crossing the plurality of gate lines; An insulating layer provided between the plurality of gate lines and the plurality of source lines; A plurality of switching elements respectively connected to the plurality of gate lines, the plurality of source lines, and the plurality of pixel electrodes; And a short ring provided in a peripheral area adjacent to the display area, a plurality of first test signal voltage input terminals, and a plurality of depleted thin film transistors DTDT, wherein the plurality of gate lines and the plurality of gate lines are provided. Each of the source lines of is connected to the short ring via each of the plurality of first inspection signal voltage input terminals and each of the plurality of depleted thin film transistors, and the plurality of depleted thin film transistors are connected to the short. Positioned between a ring and the plurality of first test signal voltage input terminals, wherein the plurality of depleted thin film transistors control a conductive state between the short ring and the plurality of gate lines and source lines. It is done. |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8279147-B2 |
| priorityDate | 1997-11-14-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
| Predicate | Subject |
|---|---|
| isDiscussedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/substance/SID419544408 |
Total number of triples: 20.