http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-100298249-B1
Outgoing Links
| Predicate | Object |
|---|---|
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-0002 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76873 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76879 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76865 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76843 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-2885 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76807 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-3205 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/C25D7-12 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-3205 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-288 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/C23C18-31 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-768 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/C25D5-02 |
| filingDate | 1998-12-09-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2001-11-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate | 2001-11-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | KR-100298249-B1 |
| titleOfInvention | How to selectively fill recesses with conductive metal |
| abstract | BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for selectively plating recesses in a semiconductor structure, the method comprising: forming an electrically insulating layer on a semiconductor substrate, forming a conductive barrier on the insulating layer, and plating seed layer on the septum forming a seed layer, laminating and patterning a photoresist layer on the plating seed layer, planarizing the insulated horizontal portions by removing the horizontal portions of the seed layer between the depressions, in the depressions Removing the remaining photoresist and then plating only the seed layer by electroplating the patterned seed layer with a conductive metal using a diaphragm layer carrying current during electroplating to plate only on the seed layer. do.n n n In an alternative method, the diaphragm is stacked over the depressions in the insulator. A relatively thick resist is then formed lithographically in the field region above the septum above the depression. The plated base, or seed layer, is laminated so as to be continuous in the horizontal region of the depressions in the insulator but discontinuous in the peripheral wall of the depressions. In the absence of a seed layer at the periphery of the substrate wafer, the recess is plated using a septum for subsequent electrical contact. After electroplating, the resist is removed by a lift off process and then the exposed diaphragm is etched by RIE method or CMP. |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-101162597-B1 |
| priorityDate | 1998-01-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 40.