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filingDate 1997-07-31-04:00^^<http://www.w3.org/2001/XMLSchema#date>
grantDate 2000-11-01-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_f02ade08a6f943a7955d2a4e40c3bfaa
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publicationDate 2000-11-01-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber KR-100267102-B1
titleOfInvention Load and storage unit for vector processor
abstract The apparatus of the present invention is coupled to a requesting unit and a memory. The apparatus of the present invention includes a data path and request control circuitry. The data path is coupled to the requesting unit and the memory. The data path is for buffering the vector. Vectors contain multiple data elements of substantially similar data types. The request control circuitry is for receiving a vector memory request from a requesting unit. The request control circuitry services the vector memory request such that the vector is passed between the requesting unit and the data path via the data path.
priorityDate 1997-01-28-04:00^^<http://www.w3.org/2001/XMLSchema#date>
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