http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-100238864-B1
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c16d2144a81bfa32a665dca1e93c3d37 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-06 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C7-06 |
| filingDate | 1996-09-06-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2000-01-15-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_68119d3beb52b303fd221a83bc64690b |
| publicationDate | 2000-01-15-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | KR-100238864-B1 |
| titleOfInvention | Bit line sense amplifier of semiconductor meory device |
| abstract | A first sense amplifier circuit connected to a pair of bit lines derived from the cell array region and for pulling up one of the bit lines and a second sense amplifier circuit for pulling down the remaining one bit line, The bit line sense amplification circuit of the semiconductor memory device for preventing overshooting in the bit line mode, the bit line sense amplification circuit comprising: an internal power supply voltage generating circuit for outputting an external power supply voltage, A circuit; An external power supply for outputting a setting signal corresponding to the reference voltage level in response to a variation of an external power supply voltage applied in response to a clock signal, A control circuit; An internal power supply control circuit for outputting a buffering signal corresponding to the applied internal power supply voltage in response to the clock signal; Driving the external or internal power supply voltage applied in response to the setting signal or the buffering signal and simultaneously driving the external or internal power supply voltage during an initial period of pull-up development of the bit line to output a first driving signal, And a plurality of driver circuits for external or internal power supply for outputting a second driving signal for disabling the setting signal after a predetermined time and driving the internal power supply voltage for a final time to maintain a level state of the first driving signal And overshooting during bit line development can be prevented. |
| priorityDate | 1996-09-06-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
| Predicate | Subject |
|---|---|
| isDiscussedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/compound/CID176015 http://rdf.ncbi.nlm.nih.gov/pubchem/substance/SID450646340 |
Total number of triples: 14.