http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-100236312-B1
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_fdad00677b9268c26e005a9e03a7b9dd |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78666 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66757 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78618 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-12 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-513 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-518 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-786 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-51 |
| filingDate | 1996-08-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 1999-12-15-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_2760c4d089fca5320617839fda509d37 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_282305b6b47df087929a02bc26e03788 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_01dfd1ab23fa7590eac2fc85fa85fcae http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_1313d461908d131621bf2056d7bcac2d |
| publicationDate | 1999-12-15-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | KR-100236312-B1 |
| titleOfInvention | A method of forming a polycrystalline silicon layer, a thin film transistor including the polycrystalline silicon layer, a manufacturing method thereof, and a liquid crystal display device including the thin film transistor |
| abstract | The present invention relates to a method of forming a polycrystalline silicon layer, a thin film transistor including the polycrystalline silicon layer, a method of manufacturing the same, and a liquid crystal display device including the thin film transistor. The thin film transistor includes a non- A gate electrode formed on the amorphous silicon layer; a source contact region and a drain contact region of the polycrystalline silicon formed in the amorphous silicon layer on both sides of the gate electrode; And a source electrode and a drain electrode formed in contact with the contact region and the drain contact region, wherein the gate insulating film includes a first insulating film covering the amorphous silicon layer as a reflectance reducing film for reducing the light reflectance of the amorphous silicon layer, And the drain contact region are formed through a first insulating film covering the laser beam It characterized in that formed by the annealing process of irradiating the non-crystalline silicon layer. |
| priorityDate | 1995-09-25-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 32.