http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-100224957-B1
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_5d7576285d411d00c697e07270d2814a |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C29-022 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G01R31-3185 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K5-08 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L22-00 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C29-56 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C29-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G01R31-3185 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03K5-08 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G01R31-28 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G01R31-26 |
| filingDate | 1996-08-29-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 1999-10-15-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_468c80b1a60a96ac954393411b05c3c8 |
| publicationDate | 1999-10-15-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | KR-100224957-B1 |
| titleOfInvention | Arrangement for enabling pin contact test of semiconductor device having clamp protection circuit and test method of semiconductor device |
| abstract | The clamp circuit 10 clamping the potential of the internal node NA electrically connected to the external terminal 7 is controlled in accordance with the control signal IFG2 generated in the control circuit 30 in response to the monitor force mode activation signal TEST1 And the output of the pre-substrate generating circuit 15, which generates a predetermined internal voltage, is controlled by a control generated in the second control circuit 40 in response to the monitor force mode activation signal And selectively connected to the internal node (NA) in response to the signal.n n n By doing so, there is an effect that a pin contact test (pin contact test) and an external monitor of the internal potential and external application of the internal potential are realized in the semiconductor device provided with the clamp circuit for absorbing the surge voltage. |
| priorityDate | 1995-08-29-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
| Predicate | Subject |
|---|---|
| isDiscussedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/substance/SID451890432 http://rdf.ncbi.nlm.nih.gov/pubchem/compound/CID160304302 |
Total number of triples: 22.