http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-100209253-B1

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filingDate 1995-11-17-04:00^^<http://www.w3.org/2001/XMLSchema#date>
grantDate 1999-07-15-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_4b8734f1afe1825ce3ddbdf85db96eb2
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_f8ecb81f817554ac6dae0e01f68920ff
publicationDate 1999-07-15-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber KR-100209253-B1
titleOfInvention Current type inverter circuit, current type logic circuit and semiconductor integrated circuit
abstract The present invention obtains a current type inverter circuit and the like operating at high speed with low power consumption.n n n The reference power supply 1 has one end connected to the power supply VDD and the other end receiving the reference current Iref.n n n The drain and gate of the NMOS transistor Q1 of the current mirror circuit CM1 receive an input signal Iin as an input unit.n n n The drain of the NMOS transistor Q2 is connected as an output to the node N1 at the other end of the reference power supply 1.n n n As an input portion, the drain and gate of the NMOS transistor Q3 of the current mirror circuit CM2 are connected to the node N1, while the drain of the NMOS transistor Q4 functions as an output portion for outputting the output power Iout. .n n n Transistor TS1 1, TS2 1, and TS1, TS2 It is set to satisfy the condition of 1, where TS1 is the ratio of the size of the NMOS transistor Q2 and the NMOS transistor Q1, and TS2 is the ratio of the size of the NMOS transistor Q4 and the NMOS transistor Q3.
priorityDate 1994-11-17-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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Total number of triples: 43.