| abstract |
A plurality of ceramic substrates are stacked to form a laminate, a semiconductor chip having a FET or the like is mounted on the first ceramic substrate, and a high frequency matching circuit is formed. A ground layer is formed on the second ceramic substrate, that is, the intermediate layer, and electrical signal interference between circuit elements disposed in each of the upper and lower layers is prevented. A bias circuit is formed on the upper surface of the third ceramic substrate and a ground electrode is formed on the lower surface of the third ceramic substrate. Further, leadless electrodes are formed on the side surfaces of each ceramic substrate and on the bottom surface of the bottom of the third ceramic substrate. The high thermal conductivity of the aluminum nitride substrate, the appropriate dielectric constant, and the three-dimensional structure are used to miniaturize the entire device and reduce the unit cost. |