http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-0154287-B1

Outgoing Links

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assignee http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_526cb931f1382d6e016ee651d55e1365
classificationCPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-4916
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-28035
classificationIPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-28
filingDate 1995-06-28-04:00^^<http://www.w3.org/2001/XMLSchema#date>
grantDate 1998-12-01-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_180c1fe8e94efae5d9477e916beeb479
publicationDate 1998-12-01-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber KR-0154287-B1
titleOfInvention Gate electrode formation method of semiconductor device
abstract The present invention discloses a method for forming a gate electrode of a semiconductor device.n n n The present invention improves the reliability of the gate electrode formed using in-situ phosphor doped polysilicon, which is superior to the gate electrode formed using conventional POCl 3 doping in terms of simplicity and ease of subsequent processes. In order to increase the deposition temperature to a temperature between 580 to 620 ℃ the poly grain starts to form, it is possible to improve the reliability by reducing the stress appearing when the phase transition by the subsequent thermal process.
isCitedBy http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-20190101736-A
priorityDate 1995-06-28-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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Total number of triples: 22.