http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-0153346-B1
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_5eaea2d025d1a96a6766b321cc334b13 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F13-36 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F13-4018 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F13-40 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F13-36 |
| filingDate | 1995-05-04-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 1998-11-16-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_f49b3259c8aa9a5ba2c48fed7b7c6a99 |
| publicationDate | 1998-11-16-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | KR-0153346-B1 |
| titleOfInvention | Apparatus and method for data packing using a dynamic computer bus |
| abstract | The present invention relates to a data packing apparatus and method using a dynamic computer bus applied to a computer having an ISA bus of a PC, XT or AT type, wherein the ISA bus is a PAC (142, 152) or a packing circuit located on a user add-on card. A dynamic 32-bit bus is provided, each PAC controlling four tag registers 210,211,212,213, four input data registers 220,221,222,223, four output data registers 240,241,242,243, and an output multiplexer 250. And the four tag registers are associated with the bytes, words, and double words assigned to the PAC during a bus write cycle, the byte-high enable signal BHEN and the system address bits SA [1: 0]. ] And the four input data registers store the bytes, words, and double words assigned to the PAC during the bus write cycle. The bytes, words, and double words are transferred to the appropriate bit positions in the input data register by four control circuits 214, 215, 216, 217 controlled by the output of the decoder that decodes the output of the platform type signal CR2B2_1 and the tag register. And the four output data registers have the function of storing the outputs of the four input registers received through the encoder 234, and the output multiplexer has the function of selecting the output of the output registers. Up to two contiguous bytes are packed into 32-bit double words for output, and up to four contiguous bytes are packed into 32-bit double words for output on PC and XT platforms, using the EISA or PCI bus. Can be used in conjunction with a single computer, and the input double word is the output double word during a 32-bit EISA or PCI bus cycle. It is characterized by being provided. |
| priorityDate | 1994-05-04-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 20.