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filingDate 2019-03-25-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationDate 2021-04-08-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber JP-WO2019194007-A1
titleOfInvention Semiconductor integrated circuit equipment
abstract A layout structure for a power switch cell using a VNW FET, which has a small area and can suppress a power supply voltage drop, is provided. The power switch cell includes a switch element (23) configured to be able to switch whether or not to electrically connect the global power supply wiring and the local power supply wiring (411,413). The switch element (23) is composed of one or more VNW (Vertical Nanowire) FETs. The top electrode of the VNW FET constituting the switch element (23) is connected to the global power supply wiring.
priorityDate 2018-04-05-04:00^^<http://www.w3.org/2001/XMLSchema#date>
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