http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-WO2016194241-A1
Outgoing Links
| Predicate | Object |
|---|---|
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H05K2201-09563 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H05K2203-1476 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H05K3-423 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H05K3-42 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H05K1-113 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-12 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H05K3-40 |
| filingDate | 2015-07-14-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate | 2017-12-28-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | JP-WO2016194241-A1 |
| titleOfInvention | Wiring substrate manufacturing method |
| abstract | In this method, a wiring substrate is efficiently manufactured using an insulating substrate 1 having a through-hole 2. A seed layer 3 is formed on one surface of the insulating substrate 1, and the surface on which the seed layer 3 is formed is masked on a masking film 4. The insulating substrate 1 and the anode 5 are disposed so that the anode 5 faces the surface opposite to the surface on which the seed layer 3 of the insulating substrate 1 is formed, and electroplating is performed in the through hole 2. After forming the metal layer 8, the masking film 4 is removed, The manufacturing method of the board | substrate for wiring characterized by the above-mentioned. [Selection] Figure 1 |
| priorityDate | 2015-05-31-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 25.