| Predicate |
Object |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-16225
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-13009
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-13
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L24-16
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-13101
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L24-13
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-15173 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-31138
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-53228
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76816
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-5329
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-3065
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-5226
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-481
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-528
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76898
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-522 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-768
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-522
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-3205
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-12 |
| filingDate |
2013-07-05-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate |
2017-02-23-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
JP-WO2015001662-A1 |
| titleOfInvention |
Semiconductor device and manufacturing method thereof |
| abstract |
The first connection wiring 210 is formed by the lower layer wiring close to the semiconductor element, and the second connection wiring 220 is formed by the upper layer wiring far from the semiconductor element. Then, after forming a first opening reaching the first connection wiring 210 and a second opening reaching the second connection wiring 220 from the back surface of the silicon substrate 100 through the silicon substrate 100, the first opening and the first A first silicon through electrode 230 and a second silicon through electrode 240 are formed in each of the two openings. Thereby, the first silicon through electrode 230 for signal propagation connected to the first connection wiring 210 and the second silicon through electrode 240 for clock supply and power supply connection connected to the second connection wiring 220 can be formed. Therefore, a semiconductor device satisfying low parasitic resistance and a large allowable current can be realized. |
| priorityDate |
2013-07-05-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |