http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-WO2010029830-A1
Outgoing Links
| Predicate | Object |
|---|---|
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/Y02D10-00 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F13-1689 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F12-06 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F12-00 |
| filingDate | 2009-08-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate | 2012-02-02-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | JP-WO2010029830-A1 |
| titleOfInvention | Semiconductor device and information processing system |
| abstract | This is an easy-to-use information processing system that maintains a constant latency, is fast and low in cost, and can ensure expandability of memory capacity. An information processing system including an information processing device, a volatile memory, and a nonvolatile memory is configured. The information processing device, the volatile memory, and the non-volatile memory are connected in series, and the number of connection signals is reduced to increase the speed while maintaining the expandability of the memory capacity. The information processing apparatus measures latency and performs latency correction operation to keep the latency constant. When transferring data from the nonvolatile memory to the volatile memory, error correction is performed to improve reliability. An information processing system composed of a plurality of chips is configured as an information processing system module in which chips are stacked on top of each other and connected by a ball grid array (BGA) or wiring technology between chips. |
| priorityDate | 2008-09-12-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 28.