http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-S6468015-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_e660bf548da827fc7b4cbb1c311092d4 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8238 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-092 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-08 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03K5-13 |
| filingDate | 1987-09-08-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_216b76ce2b58c1e8c26bfeb4d9a398de |
| publicationDate | 1989-03-14-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | JP-S6468015-A |
| titleOfInvention | Delay circuit |
| abstract | PURPOSE:To constitute a circuit of equivalently smaller number of stages of inverters by effectively using the gate polysilicon parasitic resistance of an internal cell to increase the extent of delay per one stage of inverters. CONSTITUTION:The drain of a P-channel transistor TR 15 and that of an N- channel TR 16 are connected through parasitic resistances 31-34 of respective gates of a P-channel TR 26 and an N-channel TR 26 in the succeeding stage. Consequently, polysilicon gate parasitic resistances 31-34 of the inverter in the succeeding stage are added extra to the output impedance of the inverter to increase the propagation delay time per one stage of inverters. Thus, a certain extent of delay is obtained by a smaller number of stages of inverters. |
| priorityDate | 1987-09-08-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
| Predicate | Subject |
|---|---|
| isDiscussedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/substance/SID419499693 http://rdf.ncbi.nlm.nih.gov/pubchem/compound/CID3033151 |
Total number of triples: 15.