http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-S6329967-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_4af0df9a26ff4aafde7285cbd8eb12f4 |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-8238 |
| classificationIPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-088 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8238 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-08 |
| filingDate | 1986-07-24-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_615281df8c313c0e217f7faa3a7b02ad http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c2a3afea0c00f6760dbf37b16cd2ba67 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_747cbf5e57064cfbbe085b2a2da23318 |
| publicationDate | 1988-02-08-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | JP-S6329967-A |
| titleOfInvention | Manufacture of semiconductor device |
| abstract | PURPOSE:To simplify manufacturing processes, by forming a doped region having one conductivity type and serving as a channel stopper of a CMOS device for general logics simultaneously with another doped region having the same conductivity type and serving as an offset low-resistance layer of a high dielectric strength MOS device. CONSTITUTION:After a p-type well 2 is formed in an n-type silicon substrate 1, the surface of the substrate is totally covered with a thin silicon oxide (SiO2) film 7. A silicon nitride (Si3N4) 8 is then formed thereon. After that, the silicon nitride film is removed by photolithography selectively in a region where a field oxide film is to be formed. A regist pattern 9 is formed and phosphorus (P) ions are implanted so as to form an n<-> channel stopper layer 10 of a p- MOSFET for general logics and an n<-> type offset low-resistance layer 11 of a high dielectric strength n-MOSFET simultaneously. In this manner, the ion implantation processes can be simplified and a number of photolithography processes accompanied by the ion implantation processes also can be decreased, Thus, the manufacture of the devices can be facilitated. |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-H03233965-A |
| priorityDate | 1986-07-24-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 26.